1. Field of the Invention
The present invention relates to equipment for fabricating a semiconductor device, and more particularly, to a non-homogeneous or multi characterized structure of a chemical mechanical polishing (CMP) pad for use in CMP equipment, and a method for fabricating the same.
2. Description of the Related Art
Semiconductor devices are comprised of numerous integrated circuits, which are produced by selectively and repeatedly performing a series of photographic, etching, diffusive, metal deposition, and other process steps. One particular process used on mass produced semiconductor wafers is an etch-back or polishing process to fully form device patterns that are pre-set on the wafer.
A chemical mechanical polishing (CMP) process is widely used in the semiconductor manufacturing field for horizontally planarizing various kinds of layers, such as oxide layers, nitride layers, metal layers and the like, which are sequentially deposited on the semiconductor wafer to form the integrated circuits. The CMP process is mostly used to polish metal or dielectric layers.
FIG. 1 is a typical CMP apparatus used to a polish a semiconductor wafer that has completed a deposition process. In FIG. 1, a polishing support, plate or table 2 is used for supporting and rotating a CMP pad 4 positioned on the table 2. A wafer 6 is fixed and rotated by a carrier 8, which moves vertically to selectively contact the CMP pad 4, which CMP pad 4 is also rotated at the same time by table 2. A slurry mixture, which comprises a mixture of predetermined types of chemicals and other ingredients, is provided at the central point of the CMP pad 4, and then evenly distributed and coated on the upper surface of the CMP pad 4 by the rotating force of the CMP pad 4. The semiconductor wafer 6 attached to the wafer carrier 8 selectively contacts the slurry covered CMP pad 4.
As a result of the relative rotation between the wafer 6 and the CMP pad 4 and the slurry mixture on the surface of the CMP pad 4, both mechanical friction and chemical reactions take place, and the material comprising the layer to be polished is gradually removed from the surface of the wafer. As a result, a wafer is said to be planarized to a certain pre-set thickness on the surface of the wafer. It is well known that the ultimate quality of the polished state of a thin wafer depends on several factors, including, among others: (i) the mechanical friction between CMP pad 4 and wafer 6, (ii) the material and state of the CMP pad 4, (iii) the composition and distribution rate of the chemical slurry, and (iv) the evenness or uniformity of the surface of the CMP pad 4.
With long-term utilization of the CMP equipment, the surface of the CMP pad 4 will gradually show irregularities in uniformity, making it difficult, if not impossible, to effectively polish the surface of the wafer 6 to the desired degree of planarization.
Therefore, in an effort to ensure the desired degree of evenness at the surface of the wafer 6 is maintained, a conditioner 9 is generally employed to uniformly grind the surface of the CMP pad 4 at a predetermined time interval. The conditioner 9 includes a grinding apparatus, such as artificial diamond structure, and the grinding apparatus first moves vertically to contact the surface of the CMP pad 4 and then rotates along the surface of the CMP pad 4 at a high speed. The conditioner 9 rotates and moves outwardly in a radial direction along the rotating CMP pad 4, thereby performing a conditioning process to remove a predetermined thickness of the material along the entire surface of the CMP pad 4.
The CMP pad 4 is made of polyurethane based compound, with a certain life cycle, so that it is impossible to use the CMP pad 4 for an unlimited amount of time by polishing with the conditioner 9. In other words, the CMP pad 4 must be replaced with a new CMP pad after a certain period of time elapses.
As further shown in FIG. 1, the CMP pad 4 includes a lower soft pad portion 20 contacting the table 2, and an upper hard pad portion 10 which contacts the wafer 6. More particularly, as shown in FIG. 2, the lower soft pad portion 20 is deposited on an attaching part 25, which reinforces the bonding force with table 2 of the CMP equipment. The upper hard pad portion 10 is placed on the lower soft pad portion 20, with another attaching layer 15 disposed therebetween. The attaching layer 15 functions to integrate the soft and hard pads 20 and 10. For example, the xe2x80x9cIC 1000xe2x80x9d and xe2x80x9cSuba IVxe2x80x9d polishing pads produced by the RODEL Co. may be used for the hard and soft pads 10 and 20, respectively. In another embodiment as shown in FIG. 3, the lower soft pad 30 has a lower degree of hardness relative to the hardness of the lower soft pad 20 of FIG. 2. The soft pad 30 may be a xe2x80x9cFoam Padxe2x80x9d produced by the RODEL Co.
The CMP pads shown in FIGS. 2 and 3 have been generally constructed in the following manner. First, a mono-characterized or homogeneous chemical ingot is formed, say from a polyurethane based compound. The chemical ingot is then sliced into predetermined sized pads, and then bonded together.
If a polishing process is performed with the conventional CMP pads described above, CMP engineers face a problem in that there may be a difference in the polishing rates at the center and edge of a semiconductor wafer or chip. The difference in the polishing rates leads to a dishing or recess being formed, which produces an irregular surface on the polished semiconductor wafer. To alleviate the dishing phenomenon, most engineers focus on the non-uniformity of the slurry composition and the transfer rate of the slurry, or changes in the speed of the wafer, as the main causes of the problem to be corrected. They generally tend not to focus on improving the quality of a CMP pad itself.
FIG. 4 is a graph illustrating various removal rates of soft and hard pads at the center and edges of the wafer when a polishing process is performed with a conventional mono-characterized CMP pad. In FIG. 4, graphs 3a, 3b respectively indicate soft and hard pads. As shown FIG. 4, the difference in the etching rates of the hard pad at the center and edge of a wafer is more pronounced than that of the soft pad. The level of uniformity is even lower in a wafer having a large diameter of over 8 inches, as compared to a smaller diameter wafer, thereby negatively affecting the yield of products. For example, even if the amount of a interlayer dielectric 4 (ILD4) to be removed by the aforementioned CMP pad during the polishing step is very small, strong stresses may be generated and concentrated at the edge of the wafer to damage a semiconductor device pattern positioned at the edge of the wafer.
Therefore, there has been a strong demand for development of technology to improve polishing uniformity at the wafer level or chip level of a wafer, to thereby prevent or minimize dishing or recesses and any excessive damage caused to device patterns positioned at the edge of the wafer.
It is an object of the present invention to provide an improved structure of a CMP pad which can be adapted to presently utilized CMP equipment, and a method for fabricating the same.
It is another object of the present invention to provide a structure of a CMP pad to improve polishing uniformity of a wafer, and a method for fabricating the same.
It is another object of the present invention to provide a structure of a CMP pad to prevent or minimize dishing or recesses from being formed during a CMP process, and a method for fabricating the same.
It is another object of the present invention to provide a structure of a CMP pad to prevent excessive damage to device patterns at the edge of a wafer.
It is another object of the present invention to minimize failures during a CMP process and stabilize the CMP process to improve the yield of semiconductor device products.
To realize these and other objects, in a first aspect of the present invention, there is provided a multi characterized CMP (Chemical Mechanical Polishing) pad structure, which includes a lower pad and an upper pad. The lower pad includes a lower central soft pad region and a lower peripheral soft pad region formed outwardly of the lower central soft pad region, with both the lower central soft pad region and the lower peripheral soft pad region being located in the plane of the lower pad. The upper pad is disposed on the lower pad, and the upper pad includes an upper central hard pad region and an upper peripheral soft pad region formed outwardly of the upper central hard pad region, with both the upper central hard pad region and the upper peripheral soft pad region being located in the same plane of the upper pad. The lower peripheral soft pad region has a lower hardness factor relative to the lower central soft pad region, and the upper peripheral soft pad region has substantially the same hardness factor as the lower central soft pad region.
In another aspect, the present invention provides a lower pad having a lower homogeneous soft pad region, combined with the upper pad having an upper central hard pad region and an upper peripheral soft pad region formed outwardly of the upper central hard pad region. Both the upper central hard pad region and the upper peripheral soft pad region are located in the same plane of the upper pad. The upper peripheral soft pad region has substantially the same hardness factor as the lower homogeneous soft pad region.
In still another aspect, there is provided a method for fabricating a multi characterized CMP (Chemical Mechanical Polishing) pad, including preparing a first pad mixture having a first hardness, and injecting the first pad mixture into a first mold. The mixture is then cured to create a first cured ingot. A second pad mixture is prepared and injected into a second mold, peripherally formed around the first cured ingot. The second pad mixture is integrally cured to the first cured ingot to create a multi characterized ingot of a predetermined diameter. Preferably, the hardness factors for the first and second pad mixtures are different.
The multi characterized CMP pad structure and the method for fabricating the same in the present invention are advantageous in improving CMP process uniformity at the wafer level and chip level of highly integrated semiconductor devices, while at the same time stabilizing the process to increase product yields.